By Shi-Yu Huang,Kwang-Ting (Tim) Cheng
the second one a part of the ebook supplies an intensive survey of past and fresh literature on layout mistakes prognosis and layout blunders correction. This half additionally offers an in-depth research of the algorithms utilized in common sense debugging software program courses, ErrorTracer and AutoFix, constructed via the authors.
From the Foreword:
`With the adoption of the static sign-off method of verifying circuit implementations the application-specific built-in circuit (ASIC) will adventure the 1st radical methodological revolution because the adoption of good judgment synthesis. Equivalence checking is among the severe components of this methodological revolution. This e-book is well timed for both the dressmaker trying to greater comprehend the mechanics of equivalence checking or for the CAD researcher who needs to enquire well-motivated learn difficulties reminiscent of equivalence checking of retimed designs or errors prognosis in sequential circuits.'
Kurt Keutzer, college of California, Berkeley
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Extra resources for Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing)
Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing) by Shi-Yu Huang,Kwang-Ting (Tim) Cheng